The present invention relates to a semiconductor device having a stacked type IC that requires a thinner package, and more particularly relates to a stacked type CSP (Chip Size Package).
In pursuit of a semiconductor integrated circuit of a more compact size with a higher integration, a semiconductor package also requires to be reduced in size. A CSP (Chip Size Package) provides a useful structure that requires a small mounting area and therefore satisfies the requirements described above.
A stacked type CSP is attracting attention as one of the packages applicable to a highly integrated IC.
FIG. 7 shows a cross section of a structure of a conventional stacked type CSP. A base substrate 100 has a size that is about the size of a chip. Two IC chips 101 and 102 that are stacked one on top of the other are mounted on a main surface of the base substrate 100 through insulation adhesive members 99. A plurality of conductive patterns 103 and a plurality of vias 104 are provided on the main surface of the base substrate 100. External terminals 105 such as solder balls to be connected to the respective vias 104 are provided on a rear surface of the base substrate 100.
On the side of the main surface of the base substrate 100, electrode pads 111 and 112 of the stacked IC chips 101 and 102 are electrically connected in a specified manner to the base substrate 100 through bonding wires (gold wires) 104. It is noted that the IC chip 102 has a size that does not overlap the electrode pads 111 that are provided around the IC chip 101, and is fixedly adhered to the first IC chip by the adhesive member 99. The stacked IC chips 101 and 102 and the electrical connection structure are sealed by a sealant resin 106 to thereby form a package.
As described above, the conventional stacked type CSP has a stacked structure in which the base substrate 100 that forms a mounting surface, the first IC chip 101, the second IC chip 102 and the adhesive members 99 for fixedly adhering them together are stacked one on top of the other. The thickness of the semiconductor package is determined by the stacked structure.
It is noted that the thickness of the semiconductor package is considered to be an important factor when it is mounted on a hand-carry type device, and therefore a further reduction in size and thickness of a semiconductor package is sought. As some of the measures to make an entire package thinner, the base substrate 100 is reduced in size and thickness, and each of the IC chips 101 and 102 is cut down in thickness within a range that does not affect their reliability.
However, a high level of technique is required to reduce the size and thickness of the base substrate 100 due to the complexity of the conductive patterns provided for the IC chips 101 and 102. Also, the IC chips would likely break because the IC chips are made thinner by cutting the IC chips. As a result, the manufacturing process before the packaging process becomes difficult to handle, and the manufacturing facility requires modifications.
However, the measures described above would present their limitations before they can effectively work in reducing the package in thickness. In other words, a stacked type CSP cannot be sufficiently reduced in size and thickness, while there are greater risks such as a lowered reliability in the manufacturing process, a higher cost, and the like.
The present invention has been made in view of the situations described above. It is an object of the present invention to provide a semiconductor device that can reduce its package in size and thickness by modifications of the configuration of the package while maintaining the high reliability of each of the stacked IC chips.
A semiconductor device in accordance with the present invention comprises a first IC chip having a main surface as a mounting surface on which electrode pads are provided, the main surface being externally exposed and provided with external terminals, a second IC chip that is stacked through an insulation member on a rear surface opposite to the main surface of the first IC chip, a wiring substrate for the second IC chip provided around the first IC chip, external terminals for the second IC chip provided on a mounting surface of the wiring substrate, and a sealant member that seals the second IC chip and electrical connection components therefor with the wiring substrate.
In accordance with the present invention, the first IC chip is not sealed, and only the second IC chip is sealed. Only wirings for the second IC chip may be considered for the wiring substrate. As a result, the sealant member becomes thin, but the wiring substrate has the same thickness as that of the first IC chip and therefore does not present any problem in its structural strength. Also, a protection member covers at least the electrical connection components for the second IC chip. This provides a structure in which the entire second IC chip may not necessarily be sealed.